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-- Company: 
-- Engineer: 
-- 
-- Create Date:    11:35:51 10/15/2008 
-- Design Name: 
-- Module Name:    overflow_RX - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;

entity overflow is
    Port ( clk, baud_clk, data_1, data_16 : in  STD_LOGIC;
           reset_RX : out  STD_LOGIC := '0');
end overflow;
Architecture gedrag of overflow is
	type stand is (S1,S2,S3a,S3b);
	signal v_t,h_t : stand;
	signal OK		: std_logic := '0';
	signal teller 	: integer range 0 to 4095 := 0;
	constant ES 	: integer := 3000; --16*15*10*1,25
	
begin
	comb: process (data_1,data_16,h_t,teller)
		begin
			case h_t is
			when S1 => 	if data_1 = '1' then v_t <= S2; else
							v_t <= S1; end if; 
			when S2 => 	if data_1 = '0' then v_t <= S1; 
							elsif teller >= ES then v_t <= S3a; 
							elsif data_16 = '1' then v_t <= S3b; 
							else v_t <= S2; end if;
			when S3a => if data_1 = '0' then v_t <= S1; else 
							v_t <= S3a; end if;
			when S3b => if data_1 = '0' then v_t <= S1; else 
							v_t <= S3b;  end if;
			when others => v_t <= S1;
			end case;
	end process comb;
	
	seq: process (clk)
		begin	
			if rising_edge(clk) then
				h_t <= v_t; end if;
	end process seq;
	
	output: process(baud_clk)
		begin
			if rising_edge(baud_clk) then
				if h_t = S1 then teller <= 0; else
					if h_t = S2 then teller <= teller + 1;
					end if;
				end if;
			end if;
	end process output;
	
	output_ok : process (h_t)
		begin
			if h_t = S1 then OK <= '0'; Reset_RX <= '0'; else
				if h_t = S3a then reset_RX <= '1'; else
					if h_t = S3b then OK <= '1'; 
					end if; 
				end if; 
			end if;
		end process;
end gedrag;

--package
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

package overflow_pack is
	component overflow is
		Port ( 	clk, baud_clk, data_1, data_16 : in  STD_LOGIC;
					reset_RX : out  STD_LOGIC);
end component;
end package;